32186 datasheet(610/1032 Pages) RENESAS

610 / 1032 page

SERIAL INTERFACE

12-62

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.9 Notes on Using UART Mode

• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register

The SIO Transmit/Receive Mode Register, SIO Special Mode Register and SIO Baud Rate

the serial interface is not operating. If a transmit or receive operation is in progress, wait until the

transmit and receive operations are finished and then clear the transmit and receive enable bits

before making changes.

• Settings of Baud Rate Register (SnBAUR)

Writes to the SIO Baud Rate Register take effect in the next cycle after the BRG counter has

finished counting. However, if the register is accessed for write while transmission and reception

are disabled, the written value takes effect at the same time it is written.

• Transmission/reception using DMA

To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by

setting the DMA Mode Register) before serial communication starts.

• About overrun error

If all bits of the next received data have been set in the SIO Receive Shift Register before reading

out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored

in the receive buffer register, with the previous received data retained in it. Once an overrun error

occurs, although a receive operation continues, the subsequent received data is not stored in the

receive buffer register. Before normal receive operation can be restarted, the receive enable bit

must be temporarily cleared. And this is the only way that the overrun error flag can be cleared.

• Flags showing the status of UART receive operation

There are following flags that indicate the status of receive operation during UART mode:

• SIO Receive Control Register receive status bit

• SIO Receive Control Register reception finished bit

• SIO Receive Control Register receive error sum bit

• SIO Receive Control Register overrun error bit

• SIO Receive Control Register parity error bit

• SIO Receive Control Register framing error bit

The manner in which the reception finished bit and various error flags are cleared differs depending

on whether an overrun error occurred, as described below.

[When an overrun error did not occur]

Cleared by reading out the lower byte of the receive buffer register or by clearing the receive enable bit.

[When an overrun error occurred]

Cleared by only clearing the receive enable bit.

• Switching from general-purpose port to serial interface pin

When switching from general-purpose port to the serial interface pin by the port operation mode

12.9 Notes on Using UART Mode

32186 Datasheet(PDF) 610 Page - Renesas Technology Corp