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32186 Datasheet(PDF) 609 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 609 Page - Renesas Technology Corp |
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609 / 1032 page ![]() SERIAL INTERFACE 12 12-61 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 12.8 Fixed Period Clock Output Function When using SIO0, SIO1, SIO4 or SIO5 in UART mode, the relevant port (P84, P87, P105 or P93) can be switched for use as an SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin, respectively. That way, a BRG output clock divided by 2 can be output from the SCLKO pin. Note: • This clock is output not just during data transfer. 12.8 Fixed Period Clock Output Function Figure 12.8.1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmission/reception ST SP Data ST SP Data 50% 50% BRG period Internal BRG output SCLKO output 1. Configuration when using BRG/2 clock 2. Operation timing |
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