32186 datasheet(729/1032 Pages) RENESAS

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CAN MODULE

13-119

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Synchronization

Segment

Propagation Segment

Phase Segment1

Phase Segment2

(1)

(2)

(3)

Sampling Point

• This diagram shows the bit timing when one bit consists of 8 Tq's.

• If one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the

value of the bit.

• If three-time sampling is selected, the value of the bit is determined by majority from CAN bus

values sampled at Sampling Points (1), (2) and (3).

1Tq

1 Bit

13.4 Initializing CAN Module

Figure 13.4.1 Example of Bit Timing

2) Setting the number of times sampled

Select the number of times the CAN bus is sampled from “one time” and “three times.”

• If one-time sampling is selected, the value sampled at only the end of Phase Segment1 is assumed to

be the value of the bit.

• If three-time sampling is selected, the value of the bit is determined by majority from three sampled values,

one sampled at the end of Phase Segment1 and the other sampled 1 Tq before and 2 Tq’s before that.

(8) Setting the ID mask registers

Set the values of ID mask registers (Global Mask Register, Local Mask Register A and Local Mask Register

B) that are used in acceptance filtering of received messages.

(9) Settings for use in BasicCAN mode

• Set the CAN Frame Format Select Register IDE30 and IDE31 bits. (We recommend setting the same value in

these bits.)

• Set IDs in message slots 30 and 31.

• Set the Message Control Registers 30 and 31 for data frame reception (H’40).

(10) Settings for use in single-shot mode

Using the CAN Mode Register (CAN0MODE, CAN1MODE) and CAN Control Register (CAN0CNT, CAN1CNT),

select CAN module operation mode (BasicCAN, loopback mode) and the clock source for the timestamp

counter.

(11) Setting CAN module operation mode

In the CAN Single-Shot Mode Control Register, set the slot that is to be operated in single-shot mode.

(12) Releasing CAN module from reset

When settings (1) through (11) above are finished, clear the CAN Control Register (CAN0CNT,

CAN1CNT)’s forcible reset (FRST) and reset (RST) bits to "0." Then, after detecting 11 consecutive reces-

sive bits on the CAN bus, the CAN module becomes ready to communicate.

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