32186 datasheet(751/1032 Pages) RENESAS

751 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-3

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table 14.1.3 DMA Transfer Request Generation Function of the DRI

DMA Transfer Request of the DRI

DMAC Input Channel

DIN0 event detection

DMA0

DIN1 event detection

DMA1

DIN2 event detection

DMA2

DIN3 event detection

DMA3

DIN4 event detection

DMA4

DIN5 event detection

DMA9

DEC0 underflow

DMA5

DEC1 underflow

DMA6

DEC2 underflow

DMA7

DEC3 underflow

DMA8

DEC4 underflow

DMA9

DRI address counter 0 transfer completed

DMA6

DRI address counter 1 transfer completed

DMA7

DRI capture event counter underflow

DMA8

DRI transfer counter underflow

DMA9

14.1 Outline of Direct RAM Interface (DRI)

Figure 14.1.1 Block Diagram of the Direct RAM Interface (DRI)

DD0-DD31

DRI capture control circuit

& DRI transfer control circuit

DRI data capture event

number setting register

DRI capture event counter

DRI transfer counter

DRI address counter1

DRI address reload

DRI address counter 0

DRI address reload

32bit Data Buffer

32bit data buffer

(4 stages)

DEC0

DEC1

DEC3

DEC2

DEC4

S : Selecter

DIN0

DIN1

DIN2

DIN3

DIN4

DIN0

DIN1

DIN2

DIN3

DIN4

TIO8(F/F19)

TOP8(F/F8)

TOU0_7(F/F28)

TOU1_7(F/F36)

DIN5

Event detection circuit

(DIN0

−DIN5)

DD input pin

select circuit

(DD input enable/

disable control)

DRI event counters

DRI event detection interrupt request

(DIN0

−DIN5 event detection)

DRI counter interrupt request

(DEC0

−DEC4 underflow)

DRI transfer interrupt request

(DRI address counter 0 transfer completed

DRI address counter1 transfer completed

Overrun error

Capture enable error

DRI transfer counter underflow)

DRI address bus

(To the internal RAM)

DRI data bus

(To the internal RAM)

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