32186 datasheet(754/1032 Pages) RENESAS

754 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-6

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.1 DD Input Pin Select Register

DD Input Pin Select Register (DDSEL)

<Address: H'0080 052B>

b15

DD03SEL

Bit Name

Function

8–14

No function assigned. Fix to "0."

DD03SEL

0: DD0

P127/TCLK3/CS3#/DD0

DD0–3 input pin select bit

DD1

P126/TCLK2/CS2#/DD1

DD2

P125/TCLK1/A10/DD2

DD3

P124/TCLK0/A9/DD3

1: DD0

P107/TO15/RXD4/DD0

DD1

P106/TO14/TXD4/DD1

DD2

P105/TO13/SCLKI4/SCLKO4/DD2

DD3

P104/TO12/TIN25/DD3

(1) DD03SEL(DD0–3 Input Pin Select) bit (Bit 15)

About 16 high-order bits of DDn(n= 0 to 31)which is data input to DRI, pins can be selected from two

groups(pin groups A and B).

Which pin groups (pin groups A or B) is used is selected in the DDSL (DD input 16 high-order bit pin

select) bit of DRI Data Capture Control Register (DRIDCAPCNT).In this DDSEL register, it selects

which pin is used for DD0 to DD3 when pin group A is selected.

In the DDSL bit of DRIDCAPCNT register when pin group B is selected, setting of this DDSEL register

is ignored.

In order to use pin function as DD input pin, port operation mode register also needs to be set up

separately. Pin group table is shown in Table 14.2.2.

14.2 DRI Related Registers

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