32186 datasheet(755/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-7

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.2 DRI Interrupt Related Registers

The DRI interrupt related registers are used to control the interrupt request signals output to the Interrupt

Controller from the DRI.

(1) Interrupt request status bit

This status bit is used to determine whether an interrupt is requested. When an interrupt request

occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0."

Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaf-

fected by the interrupt request enable bit, it can also be used to inspect the operating status of periph-

eral functions. In interrupt handling, make sure that within the grouped interrupt request status, only

the status bit for the interrupt request that has been serviced is cleared. If the status bit for any

interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simul-

taneously with its status bit.

(2) Interrupt request enable bit

This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set

this bit to "1" to enable interrupt requests or "0" to disable interrupt requests.

Figure 14.2.1 Interrupt Request Status and Mask Registers

14.2 DRI Related Registers

To the Interrupt Controller

Interrupt request from

each peripheral function

Interrupt request status

Data bus

Set

• Group interrupt

Interrupt request enable

clear

F/F

Data = 0

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