32186 datasheet(757/1032 Pages) RENESAS

757 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-9

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DIN Interrupt Request Status Register (DRIDINIST)

<Address: H'0080 2000>

123456

DIN0IS

DIN1IS

DIN2IS

DIN3IS

DIN4IS

DIN5IS

000000

Bit Name

Function

DIN0IS

0: Interrupt not requested

R(Note 1)

DIN0 interrupt request status bit

1: Interrupt requested

DIN1IS

DIN1 interrupt request status bit

DIN2IS

DIN2 interrupt request status bit

DIN3IS

DIN3 interrupt request status bit

DIN4IS

DIN4 interrupt request status bit

DIN5IS

DIN5 interrupt request status bit

6, 7

No function assigned. Fix to "0."

Note 1: Only writing "0" is effective. Writing "1" has no effect, so that the bit retains the previous value.

If a DINn event is detected according to settings of the DIN Input Processing Control Register, the status

bit corresponding to that DINn is set to "1" in hardware.

Note: • If the status is cleared in software at the same time it is set for an interrupt request generated,

the latter has priority, so that the status is set.

DIN Interrupt Request Enable Register (DRIDINIEN)

<Address: H'0080 2001>

b15

DIN0IEN DIN1IEN DIN2IEN DIN3IEN DIN4IEN DIN5IEN

000000

Bit Name

Function

DIN0IEN (DIN0 interrupt request enable bit)

0: Mask (disable) interrupt request

DIN1IEN (DIN1 interrupt request enable bit)

1: Enable interrupt request

DIN2IEN (DIN2 interrupt request enable bit)

DIN3IEN (DIN3 interrupt request enable bit)

DIN4IEN (DIN4 interrupt request enable bit)

DIN5IEN (DIN5 interrupt request enable bit)

14, 15

No function assigned. Fix to "0."

This register disables or prohibit the interrupt requests that will be generated for DINn event detection.

Setting each bit in this register to "1" enables the corresponding DINn event detection interrupt request.

14.2 DRI Related Registers

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