32186 datasheet(760/1032 Pages) RENESAS

760 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-12

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(5) DTRFIS (DRI Transfer Counter Interrupt Request Status) bit (Bit 4)

This bit is set when DRI transfer counter(DRITRMCT) is underflown (H'0000 0000: stop counting).

Note: • If the status is cleared in software at the same time it is set for an interrupt request generated,

the latter has priority, so that the status is set.

DRI Transfer Interrupt Request Enable Register (DRITRMIEN)

<Address: H'0080 2005>

b15

ADR0IEN ADR1IEN OVREIEN DCPEIEN DTRFIEN

00000

Bit Name

Function

ADR0IEN

0: Mask (disable) interrupt request

DRI address counter 0 interrupt request enable bit

1: Enable interrupt request

ADR1IEN

DRI address counter 1 interrupt request enable bit

OVREIEN

Overrun error interrupt request enable bit

DCPEIEN

Capture enable error interrupt request enable bit

DTRFIEN

DRI transfer counter interrupt request enable bit

13–15

No function assigned. Fix to "0."

This register enables or prohibit the interrupt requests that will be generated by the DRI transfer related

interrupt status register.

Setting any bit in this register to "1" enables the corresponding interrupt request.

14.2 DRI Related Registers

32186 Datasheet(PDF) 760 Page - Renesas Technology Corp