32186 datasheet(762/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-14

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(3) ADST (Address Counter Status) bit (Bit 2)

This bit indicates which DRI address counter, 0 or 1, is currently selected to specify the destination

address of DRI transfer.

(4) ADMD (Address Counter Operation Mode Select) bit (Bit 3)

This bit selects operation modes of DRI address counter 0(DRIADR0CT) and DRI address counter

1(DRIADR1CT). Both DRI address counters operate in the same mode.

• When continuous mode is selected

The active DRI address counter is incremented by 4 each time a DRI transfer is completed after

DRI transfer is enabled. In continuous mode, no DRI address reload register values are used.

• When reload mode is selected

When the DCPEN (capture enable) bit in the DRI Data Capture Control Register(DRIDCAPCNT)

changes state from "0" to "1" (= enabled) after DRI transfer is enabled, the DRI address counter is

reloaded with a count value from the corresponding DRI address reload register. Thereafter, the

active DRI address counter is incremented by 4 each time a DRI transfer is completed.

Note: • If the bus width for the input data from external devices is chosen to be 8 bits, a DRI transfer is

executed every four data capture events detected. Similarly, a DRI transfer is executed every

two data capture events detected if the selected bus width is 16 bits or every data capture event

detected if the selected bus width is 32 bits.

(5) ADSL (Address Counter Select) bits (Bits 4, 5)

The DRI contains two address counters to specify the internal RAM address to which data is trans-

ferred. These bits are used to select one of the two address counters.

1) When DRI address counter 0 selected

Data is transferred to the internal RAM address specified by DRI address counter 0(DRIADR0CT).

2) When DRI address counter 1 selected

Data is transferred to the internal RAM address specified by DRI address counter 1(DRIADR1CT).

3) When DRI address counters 0 and 1 toggled

The DRI address counters are switched over in hardware by an event selected by the ADEV

(address counter switchover select) bit. After a mycrocomputer reset, DRI address counter 0

(DRIADR0CT) is active. When the DRST (DRI reset) bit is cleared to "0," the active DRI address

counter is initialized to DRI address counter 0(DRIADR0CT).

(6) ADEV (Address Counter Switchover Select) bit (Bit 7)

This bit is effective only when the ADSL(address counter select) bit are set to "10" (DRI address

counters 0/1 toggled). This bit selects an event that causes the DRI address counter 0(DRIADR0CT)

and 1(DRIADR1CT) that specify the destination address on the internal RAM of transfer to switch over.

Note: • If a DEC4 underflow is selected as the address counter switchover event, it is prohibited

to select DIN4 event detection/capture event as the DEC4 count event.

14.2 DRI Related Registers

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