32186 datasheet(759/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-11

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DRI Transfer Interrupt Request Status Register (DRITRMIST)

<Address: H'0080 2004>

123456

ADR0IS

ADR1IS

OVREIS

DCPEIS

DTRFIS

00000

Bit Name

Function

ADR0IS

0: Interrupt not requested

R(Note 1)

DRI address counter 0 interrupt request status bit

1: Interrupt requested

ADR1IS

DRI address counter 1 interrupt request status bit

OVREIS

Overrun error interrupt request status bit

DCPEIS

Capture enable error interrupt request status bit

DTRFIS

DRI transfer counter interrupt request status bit

5–7

No function assigned. Fix to "0."

Note 1: Only writing "0" is effective. Writing "1" has no effect, so that the bit retains the previous value.

(1) ADR0IS (DRI Address Counter 0 Interrupt Request Status) bit (Bit 0)

If while DRI address counter 0 (DRIADR0CT) is enabled as the destination of transfer for the

captured data the DRI transfer counter (DRITRMCT) underflows (H'0000 0000: count stop) upon

reaching the terminal count, this bit is set to "1" in hardware.

(2) ADR1IS (DRI Address Counter 1 Interrupt Request Status) bit (Bit 1)

If while DRI address counter 1 (DRIADR1CT) is enabled as the destination of transfer for the

captured data the DRI transfer counter (DRITRMCT) underflows (H'0000 0000: count stop) upon

reaching the terminal count, this bit is set to "1" in hardware.

(3) OVREIS (Overrun Error Interrupt Request Status) bit (Bit 2)

The DRI contains four 32-bit intermediate buffers to avoid losses of captured data arising from bus

contention for RAM access with other bus masters. If a data capture event is detected while all of the

buffers are full, this bit is set to "1" in hardware. In this case, the detected data capture event is ignored.

(4) DCPEIS (Capture Enable Error Interrupt Request Status) bit (Bit 3)

If the DCPEN (capture enable) bit in the DRI Data Capture Control Register (DRIDCAPCNT)

changes state from "0" to "1" or the external event is detected before the DRI capture event counter

(DRIDCAPCT) or the DRI transfer counter (DRITRMCT) underflows(H'0000 0000: count stop), this

bit is set to "1."

[Set condition]

1. If any capture enable external event is selected by DEXSL(capture enable external source

select) bit in the DRI Data Capture Control Register (DRIDCAPCNT); and

1) when the selected external event is detected while DCPEN(capture enable) bit is enabled

for data capture

2) when the selected external event is detected before the DRI transfer counter (DRITRMCT)

underflows(H'0000 0000: count stop)

2. If DCPEN (capture enable) bit is set to "1" from "0" in software before the DRI transfer counter

(DRITRMCT) underflows(H'0000 0000: count stop)

Notes: • In case of 1, the capture enable event is ignored.

• In case of 2, the DRI control unit should be initialized by clearing the DRI Transfer

Control Register(DRITRMCNT) and DRI Data Capture Control Register

(DRIDCAPCNT) to "0."

14.2 DRI Related Registers

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