32186 datasheet(763/1032 Pages) RENESAS

763 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-15

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.4 DRI Special Mode Control Register

Selecting the special mode allows the DRI to be interfaced with external devices at still higher speed.

The width of input data bus during special mode is 8 or 16 bits. And data capturing timing(shown in Figure

14.2.6) can be selected when default timing. DI3 can only be selected for data synchronous signal.

Also, the event detection unit and data capture unit of the DRI are clocked by a signal whose transfer rate

has been halved as shown in Figure 14.2.5.

DRI Special Mode Register (DRISPMOD)

<Address: H'0080 2007>

b15

SPSSL

SPISL

SPMEN

Bit Name

Function

SPSSL

0: Rising edge

DIN3 sampling edge select bit

1: Falling edge

No function assigned. Fix to "0."

SPISL

0: "L" level

Special mode control unit initialization DIN1 level select bit 1: "H" level

SPMEN

0: Special mode off

Special mode enable bit

1: Special mode on

12–15

No function assigned. Fix to "0."

(1) SPSSL (DIN3 Sampling Edge Select) bit (Bit 8)

Select the falling edge as the sampling edge for the transfer method shown in Figure 14.2.4, or the

rising edge for the transfer method shown in Figure 14.2.3. This bit can only be changed while the

DRST(DRI reset) bit in DRI transfer control register(DRITRMCNT) is "0." Note that the data syn-

chronous signal during special mode is fixed to DIN3, and cannot be changed. In special mode,

furthermore, the signal controlled by DIN3ED (DIN3 event detection control) bit in the DIN Input

Processing Control Register(DINCNT) is the “output signal to the event detection unit” shown in

Figure 14.2.5, and not the input signal from the DIN3 pin.

(2) SPISL (Special Mode Control Unit Initialization DIN1 Level Select) bit (Bit 10)

The special mode control circuit block can be initialized using the input signal supplied from DIN1.

This bit selects the active level of the DIN1 signal by which said circuit is initialized. When DIN1 is

driven to the initialization level, the output signals to the event detection unit and data capture unit

all go "L," causing data sampling to stop. Conversely, when DIN1 is not at the initialization level,

data sampling is performed at given internals and the signal shown in Figure 14.2.5 is passed to the

event detection unit/data capture unit. Note that initialization function of the special mode control

circuit block by DIN1 is not affected by setting of the DIN1ED bit in the DIN Input Processing Regis-

ter (DINCNT). Note also that this bit can only be changed when the DRST (DRI reset) bit in the DRI

Transfer Control Register (DRITRMCNT) = "0."

Note: • If DIN1 changes to the initialization level while the DCPEN (capture enable) bit in the

DRI Data Capture Control Register (DRIDCAPCNT) = "1," the following problems may

occur:

1) Erroneous data is taken in by the DRI.

2) Eight data prior to a change to the reset state are not taken in.

14.2 DRI Related Registers

32186 Datasheet(PDF) 763 Page - Renesas Technology Corp

32186 Datasheet(HTML) 763 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL