32186 datasheet(766/1032 Pages) RENESAS

766 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-18

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.5 DRI Data Capture Control Register

DRI Data Capture Control Register (DRIDCAPCNT)

<Address: H'0080 2008>

123456789

b15

DCPSL

0000000000000000

DDSL

DCPEN

DEXSL

DWDSL

DDSSL

DTMSL

DWRPR

Bit Name

Function

DCPEN

0: Disable capturing data

Capture enable bit

1: Enable capturing data

1–3

DEXSL

0XX: No external source selected

Capture enable external source select bit

100: DIN0 event detection

101: DIN1 event detection

110: DIN2 event detection

111: DEC0 underflow

4, 5

DDSSL

00: No disable source selected

Capture external control disable souce select bit

01: DRI capture event counter underflow

10: DEC3 underflow

11: DEC4 underflow

6, 7

DWDSL

00: 8 bits

Input data bus width select bit

01: 16 bits

10: 32 bits

11: Settings inhibited

8, 9

DCPSL

00: DIN2 event detection

Capture event select bit

01: DIN3 event detection

10: DIN4 event detection

11: DIN5 event detection

DDSL

0: Select pin group A

DD input 16-high order bit pin select bit

1: Select pin group B

DWRPR

0: Enable WR

Capture control WR protect bit

1: Disable WR

12–15

DTMSL

0000: Default

Capture timing select bit

0001: 1 BCLK later

0010: 2 BCLK later

0011: 3 BCLK later

0100: 4 BCLK later

0101: 5 BCLK later

0110: 6 BCLK later

0111: 7 BCLK later

1000: 8 BCLK later

1001: 9 BCLK later

1010: 10 BCLK later

1011: 11 BCLK later

1100: 12 BCLK later

1101: 13 BCLK later

1110: 14 BCLK later

1111: 15 BCLK later

Note: • This register must always be accessed halfword (in 16 bits) units from the halfword boundary.

This register is used to make settings necessary to capture the input data that is fed in synchronously with an

external clock signal. Before setting up this register, make sure the DRST (DRI reset) bit in the DRI Transfer

Control Register (DRITRMCNT) is set to "1." Also, if the DRST bit is cleared to "0," be sure to clear this

14.2 DRI Related Registers

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