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32186 Datasheet(PDF) 764 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 764 Page - Renesas Technology Corp |
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764 / 1032 page ![]() DIRECT RAM INTERFACE (DRI) 14 14-16 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 (3) SPMEN (Special Mode Enable) bit (Bit 11) This bit selects whether to operate in special mode. If operation is special mode is selected, the following limitations apply. A) DRI Data Capture Control Register (DRIDCAPCNT) 1) DWDSL (Input data bus width select) bit The data width that can be handled in special mode is limited to 8 or 16 bits. According to the handled data width, set the DWDSL bits as follows: • If the input data is 8 bits wide, set the DWDSL bits to "01" (= 16 bits). • If the input data is 16 bits wide, set the DWDSL bits to "10" (= 32 bits). 2) DCPSL (Capture event select) bit Select DIN3. 3) DTMSL (Capture timing select) bit Select the default timing. B) DIN Input Processing Control Register (DINCNT) 1) DIN3ED(DIN3 event detection control) bit Select falling detection. Note: • This register can only be set while the DRST (DRI reset) bit in the DRI Transfer Control Register (DRITRMCNT) = "0," i.e., while the DRI is reset. 14.2 DRI Related Registers |
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