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32186 Datasheet(PDF) 765 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 765 Page - Renesas Technology Corp |
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765 / 1032 page  DIRECT RAM INTERFACE (DRI) 14 14-17 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 Figure 14.2.3 Data Transfer Method 1 Data Data synchronous signal Figure 14.2.4 Data Transfer Method 2 Data Data synchronous signal Figure 14.2.5 Timing Chart when Special Mode is On (DIN3 Sampling Edge: Rise) DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 Output signal to the data capture unit Output signal to the event detection unit (Note 2) Data synchronous signal (DIN3) Data DIN1(Note 1) DATA0, DATA1 DATA2, DATA3 DATA4, ... Note1: When "L" level is selected in SPISL bit of DRI special mode register (DRISPMOD) Note2: Select falling detection to DIN3ED(DIN3 event detection control) bit of DIN input processing control register (DINCNT). 14.2 DRI Related Registers |
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