32186 datasheet(767/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-19

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

(1) DCPEN (Capture Enable) bit (Bit 0)

When DCPEN = "1," the DRI is enabled for “capturing” data (i.e., taking in data into the internal RAM).

[Set condition]

• When explicitly set by writing "1" in software

• When the event selected by the DEXSL (capture enable external source select) bit is detected

[Clear condition]

• When explicitly cleared by writing "0" in software

• When the DRI capture event counter (DRIDCAPCT) underflows (H'0000 0000: stop counting)

upon reaching the terminal count

Notes: • If an external source is selected by the DEXSL (capture enable external source

select) bit, the bit cannot be set by writing "1" in software.

• Before setting the bit by writing "1" in software, always be sure to check the DRI

transfer counter (DRITRMCT) to see that the counter is in an underflow (H'0000

0000: stop counting) state.

(2) DEXSL (Capture Enable External Source Select) bits (Bits 1–3)

These bits select an external source that causes DCPEN (capture enable) bit to be enabled for data

capture. When the event selected here is detected, the capture enable bit is set to "1." If no external

sources are selected, in no case will the capture enable bit be set by any external source. The exter-

nal source or event selected by these bits can be cleared to "0" by using the DDSSL (capture external

control disable source select) bit.

(3) DDSSL (Capture External Control Disable Source Select) bits (Bits 4, 5)

These bits select the external source or event to clear the capture enable external source select bits to "0."

(4) DWDSL (Input Data Bus Width Select) bits (Bits 6, 7)

These bits select the bus width of the input data supplied from external devices. If the bus width is

chosen to be 8 bits, a DRI transfer is executed every four data capture events detected. Similarly, a

DRI transfer is executed every two data capture events detected if the selected bus width is 16 bits or

every data capture event detected if the selected bus width is 32 bits. Table 14.2.1 shows the relation-

ship between each selected bus width and the data bits that are taken in.

Note: • When special mode is selected, the input data bus width select bits are subject to setting

limitations. For details, refer to DRI Special Mode Control Register (DRISPMOD).

(5) DCPSL (Capture Event Select) bits (Bits 8, 9)

These bits select an event at which data is taken in. In cases where the DRTS (DRI reset) bit in DRI

transfer control register (DRITRMCNT)is enabled for operation, the capture enable bit is enabled for

data capture and the interleaving control is in use, data is taken in when the selected event is de-

tected while capture event detection conditions are met.If a data capture event is detected at the

same time the DCPEN (capture enable) bit is set, data is taken in.

Note: • When special mode is selected, be sure to select DIN3 event detection.

(6) DDSL (DD Input 16 High-Order Bit Pin Select) bit (Bit 10)

Of the data inputs to the DRI, DDn (n = 0–31), pins for the 16 high-order bits (DD0-DD15) can be selected

from two pin groups. This bit selects the pin group (the pin groupA,B) to be used. However, for the other

inputs DD16-DD31 are fixed. Table 14.2.2 lists pins in each pin group. If pin group A is selected, the DD

Input Pin Select Register (DDSEL) should be set to specify which pins in DD0-DD3 to be used.

Note: • Port operation mode must be set separately from this register.

14.2 DRI Related Registers

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