32186 datasheet(770/1032 Pages) RENESAS

770 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-22

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.6 DRI Data Interleave Control Register

DRI Data Interleave Control Register (DRIDSELCNT)

<Address: H'0080 200A>

123456

DSD0

DSD1

DSD2

DSD3

DSD4

00000

Bit Name

Function

DSD0

0: Not interleaved

DEC0 data interleave control bit

1: Interleaved by DEC0CT

DSD1

0: Not interleaved

DEC1 data interleave control bit

1: Interleaved by DEC1CT

DSD2

0: Not interleaved

DEC2 data interleave control bit

1: Interleaved by DEC2CT

DSD3

0: Not interleaved

DEC3 data interleave control bit

1: Interleaved by DEC3CT

DSD4

0: Not interleaved

DEC4 data interleave control bit

1: Interleaved by DEC4CT

5–7

No function assigned. Fix to "0."

The five event counters included in the DRI may be used to have the input data interleaved or “thinned

out” in hardware before being taken in. Use this register to make interleave control related settings.

If the DECn data interleave control bit (n = 0–4) is set to "0," the input data is not interleaved using the

corresponding DECn counter. If the DECn data interleave control bit is set to "1," the input data is inter-

leaved or “thinned out” because data is not taken in unless the corresponding DECn counter is in an

underflow state (count value = H'FFFF). If multiple event counters are selected for interleaving control

data by this register, data is taken in for only a capture event that is input while all of the DECn counters

with their interleave control bits set to "1" are in an underflow state.

Note: • The next event occurring after a counter underflow and those that follow are effective as the

capture event.

14.2.7 DIN Input Event Select Register

DIN Input Event Select Register (DINSEL)

<Address: H'0080 200B>

101112

b15

DIN5SL

Bit Name

Function

8–13

No function assigned. Fix to "0."

14, 15

DIN5SL

00: F/F19 (TIO8)

DIN5 input event select bit

01: F/F8 (TOP8)

10: F/F28 (TOU0_7)

11: F/F36 (TOU1_7)

The value of flip-flop, which is selected by the DIN5SL bit, is fed as an input signal to the DIN5 input

processing circuit.

14.2 DRI Related Registers

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