32186 datasheet(772/1032 Pages) RENESAS

772 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-24

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DD Input Enable Register 3 (DRIDDEN3)

<Address: H'0080 200F>

b15

DD24EN DD25EN DD26EN DD27EN DD28EN

00000000

DD29EN DD30EN DD31EN

Bit Name

Function

DD24EN (DD24 input enable bit)

0: Disable input

DD25EN (DD25 input enable bit)

1: Enable input

DD26EN (DD26 input enable bit)

DD27EN (DD27 input enable bit)

DD28EN (DD28 input enable bit)

DD29EN (DD29 input enable bit)

DD30EN (DD30 input enable bit)

DD31EN (DD31 input enable bit)

The DD Input Enable Register ‘n’ (n = 0–3) controls data input to the DRI by disabling or enabling the data

input. If the DDn input enable bit is set to "0," input to the DRI is always fixed to "0" irrespective of the

corresponding pin input level. If the DDn input enable bit is set to "1," data input to the DRI is taken in

according to the corresponding pin input level.

Figure 14.2.7 schematically shows a DD input block diagram.

Figure 14.2.7 Block Diagram of DD Input

14.2 DRI Related Registers

DDnEN(DDn input enable

)bit

DDn

DDSL bit

DDj_B

DDjEN(DDj input enable

)bit

DDj_A0

DDj_A1

DDk_B

DDkEN(DDk input enable

)bit

DDk_A

Notes: • j=0 3, k=4 15, n=16 31

•

s :Selecter

DD4-15

(To the data capture unit)

DD16-31

(To the data capture unit)

DD0-3

(To the data capture unit)

DDm

DDj_A0

DDj_A1

DD0-3 input pin select bit

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