32186 datasheet(776/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-28

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.12 DRI Address Counters

DRI Address Counter 0 (DRIADR0CT)

<Address: H'0080 2024>

DRI Address Counter 1 (DRIADR1CT)

<Address: H'0080 202C>

b15

DRIADn

0000000000000000

b16

b31

DRIADn

0000000000000000

Bit Name

Function

0–13

No function assigned. Fix to "0."

14–29

DRIADn

Destination address A14–A29

30, 31

Destination address A30, A31 (Must always be fixed to "0")

Note: • This register must always be accessed wordwise (32 bits) beginning with the word boundary(The lower address B’00).

DRI Address Counters 0 and 1 are used to specify the destination address A14–A29 in the internal RAM to

which data is DRI transferred. The address A30–A31 are fixed to "0." The counter is incremented by 4 each

time a DRI transfer finishes. DRI Address Counters have two operation modes to choose from. (For details,

refer to DRI Transfer Control Register(DRITRMCNT).

Notes: • If the DRI address counter value is outside the mapped area of the internal RAM, the

captured data is not written to any location although the DRI behaves as if a DRI transfer

had terminated normally.

• The address counter that is incremented by 4 when a DRI transfer has finished is DRI

Address Counter 0 or 1 whichever is active as set by ADSL(address counter select) bit in

the DRI Transfer Control Register(DRITRMCNT).

• These registers can only be rewritten when the DRI transfer counter(DRITRMCT) is in an

underflow state(H'0000 0000: counter stop).

14.2 DRI Related Registers

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