32186 datasheet(775/1032 Pages) RENESAS

775 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-27

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.11 DRI Transfer Counter

DRI Transfer Counter (DRITRMCT)

<Address: H'0080 2018>

b15

DRICT

0000000000000000

b16

b31

DRICT

0000000000000000

Bit Name

Function

0–13

No function assigned. Fix to "0."

14–31

DRICT

R–

DRI transfer counter

Note: • This register must always be accessed wordwise (32 bits) beginning with the address of the DRI Transfer Counter (Upper).

The DRI Transfer Counter is an 18-bit counter to count DRI transfers. When DCPEN (capture enable) bit

in DRI Data Capture Control Register(DRIDCAPCNT) changes state from data capture disabled to

enabled, this counter is reloaded with one of the values shown below, depending on how the DRI Data

Capture Event Count Setting Register(DRIDCAPNUM) and DWDSL(input data bus width select) bits in

DRIDCAPCNT register are set.

• When selected to be 8 bits, the value set in the DRI Data Capture Event Count Setting Register

(DRIDCAPNUM) divided by 4

• When selected to be 16 bits, the value set in the DRI Data Capture Event Count Setting Register

(DRIDCAPNUM) divided by 2

• When selected to be 32 bits, the value set in the DRI Data Capture Event Count Setting Register

(DRIDCAPNUM)

If the bus width for the input data from external devices is chosen to be 8 bits, a DRI transfer is executed

every four data capture events detected. Similarly, a DRI transfer is executed every two data capture events

detected if the selected bus width is 16 bits or every data capture event detected if the selected bus width is

32 bits. The counter is decremented by one each time a DRI transfer finishes. Then, when the counter

underflows(H’0000 0000), it stops counting. And Underflow of DRI transfer counter indicates H'0000

0000(counter stop).

14.2 DRI Related Registers

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