32186 datasheet(779/1032 Pages) RENESAS

779 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-31

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.15 DRI Event Counter (DEC) Control Registers

DEC0 Control Register (DEC0CNT)

<Address: H'0080 2032>

123456

DEC0EN

DEC0EXT

DEC0MOD

000000

DEC0CS

Bit Name

Function

DEC0EN

0: Disable count

DEC0 count enable bit

1: Enable count

1–3

DEC0EXT

0XX: Disable external source

DEC0 count enable source select bit

100: DIN0 event detection

101: DIN1 event detection

110: DIN2 event detection

111: Capture enable

4, 5

DEC0CS

00: DIN0 event detection

DEC0 count event select bit

01: DIN1 event detection

10: DIN2 event detection

11: DRI capture event counter underflow

No function assigned. Fix to "0."

DEC0MOD

0: Single-shot mode

DEC0 operation mode select bit

1: Continuous operation mode

DEC1 Control Register (DEC1CNT)

<Address: H'0080 2038>

123456

DEC1EN

DEC1EXT

DEC1MOD

000000

DEC1CS

Bit Name

Function

DEC1EN

0: Disable count

DEC1 count enable bit

1: Enable count

1–3

DEC1EXT

0XX: Disable external source

DEC1 count enable source select bit

100: DIN0 event detection

101: DIN1 event detection

110: DEC0 underflow

111: Capture enable

4, 5

DEC1CS

00: DIN1 event detection

DEC1 count event select bit

01: DIN2 event detection

10: DIN3 event detection

11: DEC0 underflow

No function assigned. Fix to "0."

DEC1MOD

0: Single-shot mode

DEC1 operation mode select bit

1: Continuous operation mode

14.2 DRI Related Registers

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