32186 datasheet(782/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-34

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 14.2.8 Example DEC Count Operation in Single-shot Mode

• Single-shot Mode

When DECnEN(DECn count enable) bit changes from "disabled" to "enabled," the DECn

counter(DECnCT) is loaded with the content of the DECn reload register(DECnRLD). Thereafter,

the counter counts down each time the event selected by the DECnCS (DECn count event select)

bit occurs. When event occurrences equal to the DECn Reload Register(DECnRLD) set value + 1

have been counted, the counter underflows (count value = H’FFFF) and stops counting, at which

time DECnEN(DECn count enable) bit is cleared to "0."

Notes: • The reload value loaded into the counter cannot be read out while count is enabled. If the

counter is accessed for read, the count value before being reloaded is read out.

• If the count is enabled by an external event at the same time the count source occurs, the

count enable bit is set to "1" by the external event, but the counter does not count.

• If the counter stops counting upon underflowing at the same time count is enabled by an

external event, the former has priority so that the counter stops.

• If the count is enabled by external event at the same time the count enable bit is disabled by

writing 0 in software, the latter has priority so the count is disabled.

Event count value = 6

Reload

Note 1: The reload value loaded into the counter cannot be read out while count is enabled.

If the counter is accessed for read, the count value before being reloaded is read out.

Note:

• This diagram does not show detailed timing information.

(5)

H'FFFF

(Note 1)

Count source

Count enable

Counter

Reload

Underflow signal

14.2 DRI Related Registers

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