32186 datasheet(783/1032 Pages) RENESAS

783 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-35

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Reload

H'FFFF

(Note 1)

Event count value = 4

Event count value = 3

Note 1: The reload value loaded into the counter cannot be read out while reload is generated.

If the counter is accessed for read, H'FFFF (underflow value) is read out.

Note:

• This diagram does not show detailed timing information.

Count source

Count enable

Counter

Reload

Underflow signal

Figure 14.2.9 Example DEC Count Operation in Continuous Mode

14.2 DRI Related Registers

• Continuous Operation Mode

When DECnEN(DECn count enable) bit is enabled, the counter starts counting down from the DECn

counter(DECnCT) set value each time the event selected by the DECnCS (DECn count event select)

bit occurs. Then, when the DECn counter(DECnCT) underflows (counter value = H'FFFF), the counter

is reloaded with the value of the DECn reload register(DECnRDL). Thereafter, this operation is re-

peated each time the DECn counter(DECnCT) underflows.

Notes: • When a reload occurs, the value reloaded into the counter cannot be read out. If the

counter is accessed for read, H'FFFF (underflow value) is read out.

• If the count is enabled by an external event at the same time the count source occurs, the

count enable bit is set to "1" by the external event, but the counter does not count.

• If the count is enabled by external event at the same time DECnEN(count enable) bit is

disabled by writing 0 in software, the latter has priority so the count is disabled.

• When reload and writing to counter are occured at same time, writing to counter has

priority. Interrupt by DECn counter underflow is not occured at that time.

• When count source and writing to counter are occured at same time, writing to counter has

priority. Count source is ignored at that time.

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