32186 datasheet(781/1032 Pages) RENESAS

781 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-33

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DEC4 Control Register (DEC4CNT)

<Address: H'0080 204A>

123456

DEC4EN

DEC4EXT

DEC4MOD

000000

DEC4CS

Bit Name

Function

DEC4EN

0: Disable count

DEC4 count enable bit

1: Enable count

1–3

DEC4EXT

0XX: Disable external source

DEC4 count enable source select bit

100: DIN0 event detection

101: DIN1 event detection

110: DEC3 underflow

111: Capture enable

4, 5

DEC4CS

00: DIN4 event detection

DEC4 count event select bit

01: Capture event

10: One DRI transfer completed

11: DRI transfer counter underflow

No function assigned. Fix to "0."

DEC4MOD

0: Single-shot mode

DEC4 operation mode select bit

1: Continuous operation mode

These registers are used to control the internal event counters DECn of the DRI.

(1) DECnEN (DECn Count Enable) bit (Bit 0)

This bit controls DECn count operation by enabling or disabling the count operation. This bit can be

set to "1" by an external event. Furthermore, if single-shot operation mode is selected, this bit is

cleared to "0" in hardware by a DECn counter underflow.

[Set condition to "1"]

• When explicitly set by writing "1" in software

• When the event selected by DECnEXT(DECn count enable source select) bit occurs

[Clear condition to "0"]

• When explicitly cleared by writing "0" in software

• When DECn counter underflows while operating in single-shot mode

Note: • If an external source is selected by DECnEXT(DECn count enable source select) bit,

this bit cannot be set by writing "1" in software.

(2) DECnEXT (DECn Count Enable Source Select) bits (Bits 1–3)

If DECn counter(DECnCT) needs to be enabled for counting by an external event, use these bits to select

the count enable source. When an event is detected by the selected source, DECnEN(DECn count en-

able) bit is set to "1."

(3) DECnCS (DECn Count Event Select) bits (Bits 4, 5)

These bits select the event that causes DECn counter(DECnCT) to count. When the event selected from

factor that DECnEN(DECn count enable) bit = "1" is detected, the count value of DECn counter(DECnCT)

is decremented by one.

(4) DECnMOD (DECn Operation Mode Select) bit (Bit 7)

This bit selects operation mode of DECn counter(DECnCT).

14.2 DRI Related Registers

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