32186 datasheet(778/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-30

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.14 DIN Input Processing Control Register

DIN Input Processing Control Register (DINCNT)

<Address: H'0080 2030>

b15

DIN3ED

0000000000000000

DIN0ED

DIN1ED

DIN2ED

DIN4ED

DIN5ED

Bit Name

Function

0, 1

DIN0ED

00: Input has no effect

DIN0 event detection control bit

01: Detect on rising edge

2, 3

DIN1ED

10: Detect on falling edge

DIN1 event detection control bit

11: Detect on both edges

4, 5

DIN2ED

DIN2 event detection control bit

6, 7

DIN3ED

DIN3 event detection control bit

8, 9

DIN4ED

DIN4 event detection control bit

10, 11

DIN5ED

DIN5 event detection control bit

12–15

No function assigned. Fix to "0."

Note: • This register must always be accessed in halfword (16 bit) units from the halfword boundaries.

These bits specify the event detection of the input signal as it is fed in from devices external to the DRI. The

event detection can be selected from three choices: rising edge, falling edge or both edges. The value ‘00"

(input has no effect) is selected, no events are detected. Table 14.2.3 shows the relationship between

each DINn event detection circuit and the input signals fed in from devices external to the DRI.

Note: • For the DIN3 event detection circuit, the input event signal varies depending on whether

DRI special mode is on or off.

Table 14.2.3 Relationship between Event Detection and Pins

Special Mode OFF

Special Mode ON

DIN0 event detection circuit

P130/TIN16/PWMOFF0/DIN0

DIN1 event detection circuit

P131/TIN17/PWMOFF1/DIN1

DIN2 event detection circuit

P132/TIN18/DIN2

DIN3 event detection circuit

P133/TIN19/DIN3

Output DIN3 divide by 2

DIN4 event detection circuit

P134/TIN20/TXD3/DIN4

DIN5 event detection circuit

Selected by DIN input

event select register

14.2 DRI Related Registers

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