32186 datasheet(761/1032 Pages) RENESAS

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DIRECT RAM INTERFACE (DRI)

14-13

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

14.2.3 DRI Transfer Control Register

DRI Transfer Control Register (DRITRMCNT)

<Address: H'0080 2006>

123456

DRST

DBST

ADST

ADMD

ADEV

000000

ADSL

Bit Name

Function

DRST

0: Reset DRI

DRI reset bit

1: Enable operation

DBST

0: No data exists that has not been DRI transferred yet R

–

DRI buffer status bit

1: Data exists that has not been DRI transferred yet

ADST

0: DRI address counter 0 is active

–

Address counter status bit

1: DRI address counter 1 is active

ADMD

0: Continuous mode

Address counter operation mode select bit

1: Reload mode

4, 5

ADSL

00: Select DRI address counter 0

Address counter select bit

01: Select DRI address counter 1

10: Toggle between DRI address counters 0 and 1

11: Settings inhibited

No function assigned. Fix to "0."

ADEV

0: DRI transfer counter underflow

Address counter switchover select bit

1: DEC4 underflow

(1) DRST (DRI Reset) bit (Bit 0)

This is a software reset bit of the DRI control unit. No data captures nor DRI transfers are performed

while this bit = "0." This bit should be set to "1" to enable operation of the DRI. If this bit is cleared to

"0" while the DRI is operating, the DRI capture control unit and the DRI transfer control unit both are

initialized. Therefore, if any data exists in the DRI that has not been DRI transferred yet, all transfers

for that data are canceled, and data captures are not performed either.

The following lists the registers and bits that are affected by this bit:

1) ADST(Address counter status) bit

If the DRST bit is cleared to "0" while ADSL(address counter select) bits = "10" (DRI address counters

0/1 toggled), the DRI address counter 0(DRIADR0CT) is activated and ADST bit is cleared to "0."

2) DRST(DRI buffer status) bit

If the DRST bit is cleared to "0," this status bit is initialized to "0."

3) DRI transfer counter(DRITRMCT)

If the DRST bit is cleared to "0," the DRI transfer counter(DRITRMCT) is initialized to "0."

Notes: • DIN input processing control and DEC0–4 operations are not affected by setting or

clearing the DRST bit.

• If the DRST bit changes state from "0" to "1" or vice versa, a finite time of 4 BCLKs is

required before the new state takes effect. Changing the DRST bit again during that

time is prohibited.

• If the DRST bit is set or cleared, a finite time of 1 BCLK is required before ADST bit

and DBST bit are initialized.

• Changing any of ADMD(address counter operation mode select) bit, ADSL (address

counter select) bit or ADVEN(address counter switchover select) bit while the DRST

bit = "1" is prohibited.

(2) DBST (DRI Buffer Status) bit (Bit 1)

This bit indicates whether the internal DRI buffer contains any data that has not been DRI transferred yet.

In order to avoid the data loss of Data transfer, middle buffer for 32 bits × 4 row is embedded in the

inside of DRI. If the data is in this middle buffer, DBST bit shows “1.” If it is not DBST bit shows “0”

Also, when DRST bit is “0” cleared DBST bit is cleared as well.

14.2 DRI Related Registers

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