32186 datasheet(758/1032 Pages) RENESAS

758 / 1032 page

DIRECT RAM INTERFACE (DRI)

14-10

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

DEC Interrupt Request Status Register (DRIDECIST)

<Address: H'0080 2002>

123456

DEC0IS

DEC1IS

DEC2IS

DEC3IS

DEC4IS

00000

Bit Name

Function

DEC0IS (DEC0 interrupt request stabus bit)

0: Interrupt not requested

R(Note 1)

DEC1IS (DEC1 interrupt request stabus bit)

1: Interrupt requested

DEC2IS (DEC2 interrupt request stabus bit)

DEC3IS (DEC3 interrupt request stabus bit)

DEC4IS (DEC4 interrupt request stabus bit)

5–7

No function assigned. Fix to "0."

Note 1: Only writing "0" is effective. Writing "1" has no effect, so that the bit retains the previous value.

If one of five event counters (DEC0–DEC4) included in the DRI underflows upon reaching the terminal

count, the corresponding status bit in this register is set to "1" in hardware.

Note: • If the status is cleared in software at the same time it is set for an interrupt request generated,

the latter has priority, so that the status is set.

DEC Interrupt Request Enable Register (DRIDECIEN)

<Address: H'0080 2003>

b15

DEC0IEN DEC1IEN DEC2IEN DEC3IEN DEC4IEN

00000

Bit Name

Function

DEC0IEN (DEC0 interrupt request enable bit)

0: Mask (disable) interrupt request

DEC1IEN (DEC1 interrupt request enable bit)

1: Enable interrupt request

DEC2IEN (DEC2 interrupt request enable bit)

DEC3IEN (DEC3 interrupt request enable bit)

DEC4IEN (DEC4 interrupt request enable bit)

13–15

No function assigned. Fix to "0."

This register enables or prohibit the interrupt requests that will be generated when one of the internal event

counters underflows.

Setting each bit in this register to "1" enables the interrupt request by the corresponding event counter

underflow.

14.2 DRI Related Registers

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