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32186 Datasheet(PDF) 956 Page - Renesas Technology Corp

Part # 32186
Description  MCU
PDF  1032 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

32186 Datasheet(HTML) 956 Page - Renesas Technology Corp

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23
ELECTRICAL CHARACTERISTICS
23-40
32185/32186 Group Hardware Manual
Rev.1.10 REJ09B0235-0110 May 15, 07
23.9 A.C. Characteristics (when VCCE = 5 V)
(18) DRI Timing
a) When Special mode is off
Symbol
Parameter
Rated Value
Unit
See Fig.
MIN
MAX
23.9.20
tw(DIN)
DIN Input pulse width DIN0, DIN1, DIN2, DIN3, DIN4
1.5 x tc(BCLK)
ns
[138]
tc(DCAP) Import period
When Input data bus width is 8, 16 bit
3.5 x tc(BCLK)
ns
[139]
When Input data bus width is 32 bit
4 x tc(BCLK)
ns
tsu(DD-E)
When DIN2, DIN3, DIN4 are selected
DD Input - Import Edge in Import event
20
ns
[140]
Set up time (Note 1)
When DIN5 is selected in Import event
40
ns
th(E-DD)
Import Edge - DD Input
When DIN2, DIN3, DIN4 are selected
in Import event
15 + tc(BCLK)
ns
[141]
Hold time (Note 1)
When DIN5 is selected in Import event
15 + tc(BCLK)
ns
ts(E-E)
Edge interval that
DIN0, DIN1, DIN2, DIN3, DIN4
15 + tc(BCLK)
ns
[142]
Event detection is
not simultaneous
Note 1: This standard value is when considering Import timing as a default setup. If it is not, standard value is considered with
the point that is shifted back from standard edge for tc(BCLK).
b) When Special mode is on
Symbol
Parameter
Rated Value
Unit
See Fig.
MIN
MAX
23.9.20
tw(DIN)
DIN Input pulse width
DIN0, DIN1, DIN2, DIN3, DIN4
1.5
×tc(BCLK)
ns
[138]
DIN3
0.8
×tc(BCLK)
ns
tc(DCAP) Import period
When Input data bus width is 8, 16 bit
2
×tc(BCLK)
ns
[139]
tsu(DD-E)
DD Input - Import Edge
When DIN3 is selected in Import event
20
ns
[140]
Set up time
th(E-DD)
Import Edge - DD Input
When DIN3 is selected in Import event
20
ns
[141]
Hold time
ts(E-E)
Edge interval that
DIN0, DIN1, DIN2, DIN4
15 + tc(BCLK)
ns
[142]
Event detection is
not simultaneous
tar
Indefinite period of
DIN3
Sampling Edge by DIN1 before
20
ns
[143]
exiting reset initializing level
tbr
Indefinite period of
DIN3
Sampling Edge by DIN1 after
20
ns
[144]
exiting reset initializing level



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