32186 datasheet(176/1032 Pages) RENESAS

176 / 1032 page

INTERNAL MEMORY

6-34

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

6.6 Programming Internal Flash Memory

Figure 6.6.7 Procedure for Entering Normal Mode

START

Execute flash write/erase command

and various read commands

FBUSY bit = 1

(Note 1)

YES

Execute read array command or

reset flash memory with the FRESET bit

in Flash Control Register 4 (FCNT4)

FAENS bit = 1

(Note 2)

YES

Set the FENTRY bit of the Flash

Control Register 1 (FCNT1) to 0

Wait for more than 8 CPUCLK cycles (Note 3)

END

Note 1: If it is checked that the value of FBUSY bit in Flash Status Register (FSTAT) is "1" after executing the

command in flash E/W enable mode, it is not necessary to check that the value of FBUSY bit is "1."

Note 2: If flash memory reset by FRESET bit in Flash Control Register 4 (FCNT4) is not executed, it is not

necessary to check that the value of FAENS bit in Flash Mode Register (FMOD) is "1."

Note 3: Insert any instructions for more than 8 CPUCLK waits other than NOP that do not require clock cycles

(one that is automatically inserted by the assembler for alignment adjustment: instruction code H'F000).

As the EI vector entry address is exchanged in the instructions for 8 CPUCLK waits, disenable the External

Interrupt (EI).

Note: • When switching to normal mode by entering a "L" level signal to the RESET# pin in flash E/W enable mode,

enter the signal to the RESET# pin after checking that the value of FBUSY bit is "1"(ready).

Jump to the flash memory or apply reset

Switched to normal mode

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