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32186 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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32186 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 1032 page ![]() INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8 8-13 32185/32186 Group Hardware Manual Rev.1.10 REJ09B0235-0110 May 15, 07 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) <Address: H’0080 0720> P1 Direction Register (P1DIR) <Address: H’0080 0721> P2 Direction Register (P2DIR) <Address: H’0080 0722> P3 Direction Register (P3DIR) <Address: H’0080 0723> P4 Direction Register (P4DIR) <Address: H’0080 0724> P6 Direction Register (P6DIR) <Address: H’0080 0726> P7 Direction Register (P7DIR) <Address: H’0080 0727> P8 Direction Register (P8DIR) <Address: H’0080 0728> P9 Direction Register (P9DIR) <Address: H’0080 0729> P10 Direction Register (P10DIR) <Address: H’0080 072A> P11 Direction Register (P11DIR) <Address: H’0080 072B> P12 Direction Register (P12DIR) <Address: H’0080 072C> P13 Direction Register (P13DIR) <Address: H’0080 072D> P15 Direction Register (P15DIR) <Address: H’0080 072F> P17 Direction Register (P17DIR) <Address: H’0080 0731> P22 Direction Register (P22DIR) <Address: H’0080 0736> Note: • n = 0–13, 15, 17, 22 (not including P5) <Upon exiting reset: H’00> b Bit Name Function R W 0(8) Pn0DR 0: Input mode R W Port Pn0 direction bit 1: Output mode 1(9) Pn1DR Port Pn1 direction bit 2(10) Pn2DR Port Pn2 direction bit 3(11) Pn3DR Port Pn3 direction bit 4(12) Pn4DR Port Pn4 direction bit 5(13) Pn5DR Port Pn5 direction bit 6(14) Pn6DR Port Pn6 direction bit 7(15) Pn7DR Port Pn7 direction bit Notes: • Following bits are not provided (read as 0, writing has no effect): P40, P60, P64–P67, P80, P81, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222, P223, P226, P227 • All ports are set for input mode upon exiting the reset state. • P221 is an input-only port. Fix it to "0" when write. • After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to "1" (input enable), pin level can be read after 2BCLK period. b0 12 3456 b7 (b8 9 10 11 12 13 14 b15) Pn0DR Pn1DR Pn2DR Pn3DR Pn4DR Pn5DR Pn6DR Pn7DR 000 0000 0 8.3 Input/Output Port Related Registers |
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