32186 datasheet(272/1032 Pages) RENESAS

272 / 1032 page

DMAC

9-26

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2 DMAC Related Registers

DMA0 Channel Control Register 2 (DM0CNT2)

<Address: H’0080 0481>

DMA1 Channel Control Register 2 (DM1CNT2)

<Address: H’0080 0483>

DMA2 Channel Control Register 2 (DM2CNT2)

<Address: H’0080 0485>

DMA3 Channel Control Register 2 (DM3CNT2)

<Address: H’0080 0487>

DMA4 Channel Control Register 2 (DM4CNT2)

<Address: H’0080 0489>

DMA5 Channel Control Register 2 (DM5CNT2)

<Address: H’0080 0491>

DMA6 Channel Control Register 2 (DM6CNT2)

<Address: H’0080 0493>

DMA7 Channel Control Register 2 (DM7CNT2)

<Address: H’0080 0495>

DMA8 Channel Control Register 2 (DM8CNT2)

<Address: H’0080 0497>

DMA9 Channel Control Register 2 (DM9CNT2)

<Address: H’0080 0499>

b15

000000

RINGSEL

SELFEN

Bit Name

Function

SELFEN

0: Disable self channel transfer

Self channel transfer selection

1: Enable self channel transfer

No function assigned. Fix to "0."

0–

10–15

RINGSEL

00 0000: 32-time ring buffer mode

Ring buffer select bit

10 0000: 32-time ring buffer mode

11 0000: 16-time ring buffer mode

11 1000: 8-time ring buffer mode

11 1100: 4-time ring buffer mode

11 1110: 2-time ring buffer mode

Settings other than above are inhibited

The DMA Channel Control Register 0 consists of the bits to select DMA transfer mode on each channel,

set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as

well as those to set the transfer size and the source/destination address directions.

The DMA Channel Control Register 1 consists of the bits to select a source/destination address bank and

the cause or source of extended DMA transfer request on each DMA channel.

The DMA Channel Control Register 2 consists of the bits to enable self channel transfer on each channel

and set the number of transfers in the ring buffer mode.

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