32186 datasheet(273/1032 Pages) RENESAS

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DMAC

9-27

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2 DMAC Related Registers

[DMnCNT0 Register]

(1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0)

When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer

mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode.

The number of transfers in the ring buffer mode is selected with register DMnCNT2.

(2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1)

This flag indicates if there are DMA transfer requests for each channel. This bit is set to “1,” when

DMA transfer requests are occurred in spite of TENLn bit setting value and then after completing

transmission it is cleared to “0.”

And when write “0” to this bit, it clear DMA transfer requests occurred. When write “1,” it keeps value

which before writing.

If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has

already been set to "1," the next DMA transfer request is not accepted until the transfer being per-

formed on that channel is completed.

(3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2, 3)

These bits select the cause or source of DMA transfer request on each DMA channel.

(4) TENLn (DMAn Transfer Enable) bit (Bit 4)

When setting this bit to “1” (enable transfer), DMA transfer is enable and when all transmissions are

completed (underflow of transfer count register), it is “0” cleared. And when DMA transfer request is

already occurred and set to transfer enable, DMA transfer starts immediately so that make sure not to

do that.

When setting this bit to “0” (disable transfer), DMA transfer is disable. However, if a transfer request

has already been accepted, transfers on that channel are not disabled until after the requested trans-

fer is completed.

(5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5)

This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one

transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1."

(6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6)

This bit selects the direction in which the source address changes. This mode can be selected from

two choices: Address fixed or Address incremental.

(7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7)

This bit selects the direction in which the destination address changes. This mode can be selected

from two choices: Address fixed or Address incremental.

Extended DMA transfer

request source selected

DMAn transfer

request source

DMAn

Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection

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