32186 datasheet(277/1032 Pages) RENESAS

277 / 1032 page

DMAC

9-31

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2.4 DMA Destination Address Registers

DMA0 Destination Address Register (DM0DA)

<Address: H’0080 0414>

DMA1 Destination Address Register (DM1DA)

<Address: H’0080 0424>

DMA2 Destination Address Register (DM2DA)

<Address: H’0080 0434>

DMA3 Destination Address Register (DM3DA)

<Address: H’0080 0444>

DMA4 Destination Address Register (DM4DA)

<Address: H’0080 0454>

DMA5 Destination Address Register (DM5DA)

<Address: H’0080 041C>

DMA6 Destination Address Register (DM6DA)

<Address: H’0080 042C>

DMA7 Destination Address Register (DM7DA)

<Address: H’0080 043C>

DMA8 Destination Address Register (DM8DA)

<Address: H’0080 044C>

DMA9 Destination Address Register (DM9DA)

<Address: H’0080 045C>

123456789

b15

DM0DA–DM9DA

????????????????

Bit Name

Function

0–15

DM0DA–DM9DA

Destination address bits A16–A31

(Note 1)

Note 1: A0 to A15 are fixed by DMAn Channel Control Register 1 (DMnCNT1) bits 10 and 11.

Notes: • This register must always be accessed in halfwords

• Address other than SFR area and internal RAM area must be set.

The DMA Destination Address Register is used to set the destination address of DMA transfer in such a

way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a

current register, the values read from this register are always the current value.

When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if

“Address fixed” is selected, is the same source address that was set in it before the DMA transfer began;

if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit

transfer) or the last transfer address + 2 (for 16-bit transfer).

The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an

even address. If accessed in bytes, the value in this register is undefined.

(1) DM0DA–DM9DA (Destination Address bits A16–A31)

Set this register to specify the destination address of DMA transfer in the SFR area or internal RAM

area.

For high-order 16 bits (A0 to A15) of the destination address, Bank 0 to Bank 2 are selected ac-

cording to the setting of DMAn channel control register 1 (DMnCNT1) bits 10 and 11, and the high-

order 16 bits of the corresponding destination address are fixed. In this register, the low-order 16

bits of the destination address are set. (Bit 0 and bit 15 correspond to A16 and A31 of the destina-

tion address, respectively) Note that no transfer over the bank is carried out when "increment" is

selected in SADSLn bit of DMAn channel control register(DMnCNT0). Upon completion of bank

transfer to the final address, the bank is to be transferred to the head address.

9.2 DMAC Related Registers

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