32186 datasheet(278/1032 Pages) RENESAS

278 / 1032 page

DMAC

9-32

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2.5 DMA Transfer Count Registers

DMA0 Transfer Count Register (DM0TCT)

<Address: H’0080 0416>

DMA1 Transfer Count Register (DM1TCT)

<Address: H’0080 0426>

DMA2 Transfer Count Register (DM2TCT)

<Address: H’0080 0436>

DMA3 Transfer Count Register (DM3TCT)

<Address: H’0080 0446>

DMA4 Transfer Count Register (DM4TCT)

<Address: H’0080 0456>

DMA5 Transfer Count Register (DM5TCT)

<Address: H’0080 041E>

DMA6 Transfer Count Register (DM6TCT)

<Address: H’0080 042E>

DMA7 Transfer Count Register (DM7TCT)

<Address: H’0080 043E>

DMA8 Transfer Count Register (DM8TCT)

<Address: H’0080 044E>

DMA9 Transfer Count Register (DM9TCT)

<Address: H’0080 045E>

b15

DM0TCT–DM15TCT

????????????????

Bit Name

Function

0–15

DM0TCT–DM9TCT

DMA transfer count

(Has no effect during ring buffer mode)

Note: • This register must always be accessed in halfwords.

The DMA Transfer Count Register is used to set the number of times data is transferred on each channel.

However, the value in this register has no effect during ring buffer mode.

The transfer count is the "value set in the transfer count register + 1." Because the DMA Transfer Count

(However, if the register is read in a cycle immediately after transfer, the value obtained is one that was

stored in the count register before the transfer began.) When transfer finishes, this count register

underflows and the value read from it is H’FFFF.

When transfer is enabled, this register is protected in hardware and cannot be accessed for write.

During ring buffer mode, the transfer count register counts down in free-run mode and continues counting

until transfer is disabled. No interrupt is generated at underflow.

If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all

transfers on a channel are completed (i.e., the transfer count register underflows), transfer on the cas-

caded channel starts.

The DMA Transfer Count Register must always be accessed in halfwords (16 bits) beginning with an even

address. If accessed in bytes, the value in this register is undefined.

9.2 DMAC Related Registers

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