32186 datasheet(279/1032 Pages) RENESAS

279 / 1032 page

DMAC

9-33

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.2 DMAC Related Registers

9.2.6 DMA Interrupt Related Registers

The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to

the Interrupt Controller.

(1) Interrupt request status bit

This status bit is used to determine whether there is an interrupt request. When an interrupt request

occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0."

Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is

unaffected by the interrupt request mask bit, it can be used to inspect the operating status of periph-

eral functions.

In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the

interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not

been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit.

(2) Interrupt request mask bit

This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0"

to enable interrupt requests or "1" to disable interrupt requests.

Figure 9.2.2 Interrupt Request Status and Mask Registers

To the Interrupt

Controller

Interrupt request from

each peripheral function

Interrupt request status

Data bus

Set

Group interrupt

Interrupt request enabled

clear

F/F

Data = 0

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