32186 datasheet(293/1032 Pages) RENESAS

293 / 1032 page

DMAC

9-47

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 9.3.3 Transfer Byte Positions

(7) Ring buffer mode

In the ring buffer mode, the number of DMA transfers to each channel can be selected from among 32,

16, 8, 4 and 2 times, and after transfer from the transfer start address, the bit returns to the transfer

start address again: thus, the same operation is repeated by the selected frequency.

Note: • The transfer start address must be as follows:

Transfer Size: 8 bits

Transfer Size: 16 bits

32-time ring buffer mode Low order 5 bits – B’00000

Low order 6 bits – B’000000

16-time ring buffer mode Low order 4 bits – B’0000

Low order 5 bits – B’00000

8-time ring buffer mode Low order 3 bits – B’000

Low order 4 bits – B’0000

4-time ring buffer mode Low order 2 bits – B’00

Low order 3 bits – B’000

2-time ring buffer mode Low order 1 bits – B’0

Low order 2 bits – B’00

The address increment operation in the ring buffer mode is as follows.

[1] When the transfer size is 8 bits

The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are

incremented by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they

are recycled to B’00000 by the next increment operation, thus returning to the start address again.

[2] When the transfer size is 16 bits

The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented

by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to

B’000000 by the next increment operation, thus returning to the start address again.

9.3 Functional Description of DMAC

(5) Transfer count value

The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits).

(6) Transfer byte positions

When the transfer unit is 8 bits, the LSB of the address register is effective for both source and

destination. (Therefore, in addition to data transfers between even addresses or between odd ad-

dresses, data may be transferred from even address to odd address or vice versa.) When the transfer

unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in

two bytes aligned to the 16-bit bus.

The diagram below shows the valid byte positions in DMA transfer.

b7 b8

b15

8 bits

Source

Destination

8 bits

16 bits

b7 b8

b15

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