32186 datasheet(291/1032 Pages) RENESAS

291 / 1032 page

DMAC

9-45

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Figure 9.3.2 Gaining and Releasing Control of the Internal Bus

One DMA transfer

DMAC

CPU

Internal bus arbitration

(requests from the DMAC)

Internal bus

R: Read

W: Write

Requested

Gained

Requested

Gained

Requested

Gained

One DMA transfer

Released

9.3 Functional Description of DMAC

9.3.3 Starting DMA

Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Chan-

nel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or

source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1." DMA

transfer begins when the specified cause or source of DMA transfer request becomes effective after set-

ting the TENL (DMA transfer enable) bit to "1."

Note: • If the transfer request source selected by the REQSL (DMA transfer request source select) and

REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time

required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN

input signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest.

Or, depending on the preceding or following bus usage condition, up to five cycles (250 ns when

the internal peripheral clock = 20 MHz) may be required. (However, this applies when the external

bus, HOLD and the LOCK instruction all are unused.)

To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input

signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Chapter 23 ELECTRI-

CAL CHARACTERISTICS)

9.3.4 DMA Channel Priority

DMA0 has the highest priority. The priority of this and other channels is shown below.

DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9

This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is re-

quested, the channel that has the highest priority is selected.

9.3.5 Gaining and Releasing Control of Internal Bus

For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single

transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA trans-

fer request is accepted and after executing one DMA transfer (in one read and one write peripheral clock

cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.

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