32186 datasheet(292/1032 Pages) RENESAS

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DMAC

9-46

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.3.6 Transfer Units

Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be

transferred in one DMA transfer.

9.3.7 Transfer Counts

Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed

up to 65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one

transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run

mode, with the value set in it ignored.

9.3.8 Address Space

The address space in which data can be transferred by DMA is SFR area or internal RAM area (32185: H'0080 0000

to H'0080 BFFF, 32186: H’0080 0000 to H’0081 3FFF) for both source and destination. To set the source and

destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Ad-

dress Register. Note that no transfer over the bank is carried out. Upon completion of bank transfer to the

final address, the bank is to be transferred to the head address.

9.3.9 Transfer Operation

(1) Dual-address transfer

Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read

access and the other for destination write access. (The transfer data is taken into the DMAC’s internal

temporary register before being transferred.)

(2) Bus protocol and bus timing

Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus

protocol and the same bus timing as when peripheral modules are accessed by the CPU.

(3) Transfer rate

Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the

bus and one read and one write cycles to perform one transfer. Therefore, the maximum transfer rate

is calculated by the equation below:

Maximum transfer rate [bytes per second] = 2 bytes

1/f(BCLK)

× 3 cycles

(4) Address count direction and address changes

The direction in which the source and destination addresses are counted as transfer proceeds (“Ad-

dress fixed” or “Address incremental”) is set for each channel using the SADSL (source address

direction select) and DADSL (destination address direction select) bits.

When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed;

when the transfer size is 8 bits, the address is incremented by one.

Table 9.3.11 Address Count Direction and Address Changes

Address Count Direction

Transfer Unit

Address Change for One DMA

Address fixed

8 bits

16 bits

Address incremental

8 bits

16 bits

9.3 Functional Description of DMAC

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