32186 datasheet(288/1032 Pages) RENESAS

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DMAC

9-42

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.3 Functional Description of DMAC

Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7

REQSL7

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA7 Software Request Generation Register

SIO2_TXD (transmit buffer empty)

When SIO2 transmit buffer is empty

CAN0_S1/S30

When CAN0 slot 1 transmission failed or slot 30 transmission/reception finished

Extended DMA7 transfer request

The source selected by the DMA7 Channel Control Register 1

source selected

(DM7CNT1) REQESEL7 bits (see below)

REQESEL7 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

One DMA6 transfer completed

When one DMA6 transfer is completed (cascade mode)

0001

MJT (TOU0_2irq)

MJT TOU0_2 interrupt source

0010

SIO3_TXD (transmit buffer empty)

When SIO3 transmit buffer is empty

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

DRI address counter 1 transfer completed

When DRI address counter 1 transfer completed

1110

DRI (DEC2_udf)

When DRI DEC2 underflow occurs

1111

CAN1_S1/S30

When CAN1 slot 1 transmission failed or slot 30 transmission/reception

finished

Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8

REQSL8

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA8 Software Request Generation Register

MJT (input event bus 0)

When MJT input event bus 0 signal is generated

SIO3_RXD (reception completed) When SIO3 reception is completed

Extended DMA8 transfer request

The source selected by the DMA8 Channel Control Register 1

source selected

(DM8CNT1) REQESEL8 bits (see below)

REQESEL8 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

CAN1_S0/S31

When CAN1 slot 0 transmission failed or slot 31 transmission/reception

finished

0001

MJT (TOU0_6irq)

MJT TOU0_6 interrupt source

0010

One DMA7 transfer completed

When one DMA7 transfer is completed (cascade mode)

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

DRI latch event counter_udf

When DRI latch event counter underflow occurs

1110

DRI (DEC3_udf)

When DRI DEC3 underflow occurs

1111

Settings inhibited

–

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