32186 datasheet(285/1032 Pages) RENESAS

285 / 1032 page

DMAC

9-39

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1

REQSL1

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA1 Software Request Generation Register

MJT (output event bus 0)

When MJT output event bus 0 signal is generated

Settings inhibited

–

Extended DMA1 transfer request

The source selected by the DMA1 Channel Control Register 1

source selected

(DM1CNT1) REQESEL1 bits (see below)

REQESEL1 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

One DMA0 transfer completed

When one DMA0 transfer is completed (cascade mode)

0001

MJT (TIN3S)

When MJT TIN3 input signal is generated

0010

MJT (TID1_udf/ovf)

When MJT TID1 underflow/overflow occurs

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

MJT (TOU1_1irq)

When TOU1_1 interrupt request is generated

1110

DRI (DIN1)

When DRI DIN1 event detection interrupt is generated

1111

SIO4_RXD (reception completed)

When SIO4 reception-completed interrupt is generated

Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2

REQSL2

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA2 Software Request Generation Register

MJT (output event bus 1)

When MJT output event bus 1 signal is generated

MJT (TIN18S)

When MJT TIN18 input signal is generated

Extended DMA2 transfer request

The source selected by the DMA2 Channel Control Register 1

source selected

(DM2CNT1) REQESEL2 bits (see below)

REQESEL2 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

One DMA1 transfer completed

When one DMA1 transfer is completed (cascade mode)

0001

Settings inhibited

–

0010

CAN(CAN0_S1/S30)

When CAN0 slot 1 transmission failed or slot 30 transmission/reception

finished

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

Settings inhibited

–

1110

DRI (DIN2)

When DRI DIN2 event detection interrupt is generated

1111

SIO5_TXD (transmit buffer empty)

When SIO5 transmit buffer empty interrupt is generated

9.3 Functional Description of DMAC

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