32186 datasheet(286/1032 Pages) RENESAS

286 / 1032 page

DMAC

9-40

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3

REQSL3

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA3 Software Request Generation Register

SIO0_TXD (transmit buffer empty)

When SIO0 transmit buffer is empty

SIO1_RXD (reception completed)

When SIO1 reception is completed

Extended DMA3 transfer request

The source selected by the DMA3 Channel Control Register 1

source selected

(DM3CNT1) REQESEL3 bits (see below)

REQESEL3 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

MJT (TIN0S)

When MJT TIN0 input signal is generated

0001

One DMA2 transfer completed

When one DMA2 transfer is completed (cascade mode)

0010

Settings inhibited

–

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

MJT (TOU1_6irq)

When MJT TOU1_6 interrupt request is generated

1110

DRI (DIN3)

When DRI DIN3 event detection interrupt is generated

1111

SIO5_RXD (reception completed)

When SIO5 reception-completed interrupt is generated

Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4

REQSL4

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA4 Software Request Generation Register

One DMA3 transfer completed

When one DMA3 transfer is completed (cascade mode)

SIO0_RXD (reception completed)

When SIO0 reception is completed

Extended DMA4 transfer request

The source selected by the DMA4 Channel Control Register 1

source selected

(DM4CNT1) REQESEL4 bits (see below)

REQESEL4 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

MJT (TIN19S)

When MJT TIN19 input signal is generated

0001

SIO0_TXD (transmit buffer empty)

When SIO0 transmit buffer is empty

0010

MJT (TOU1_7irq)

MJT TOU1_7 interrupt source

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

MJT (TIN7S)

When MJT TIN7 input signal is generated

1110

DRI (DIN4)

When DRI DIN4 event detection interrupt is generated

1111

Settings inhibited

–

9.3 Functional Description of DMAC

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