32186 datasheet(287/1032 Pages) RENESAS

287 / 1032 page

DMAC

9-41

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5

REQSL5

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start or one DMA7

When any data is written to the DMA5 Software Request Generation Register

transfer completed

or when one DMA7 transfer is completed (cascade mode)

All DMA0 transfers completed

When all DMA0 transfers are completed (cascade mode)

SIO2_RXD (reception completed)

When SIO2 reception is completed

Extended DMA5 transfer request

The source selected by the DMA5 Channel Control Register 1

source selected

(DM5CNT1) REQESEL5 bits (see below)

REQESEL5 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

MJT (TIN20S)

When MJT TIN20 input signal is generated

0001

MJT (TOU0_0irq)

MJT TOU0_0 interrupt source

0010

Settings inhibited

–

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

MJT (TIN8S)

When MJT TIN8 input signal is generated

1110

DRI (DEC0_udf)

When DRI DEC0 underflow occurs

1111

CAN1_S0/S31

When CAN1 slot 0 transmission failed or slot 31 transmission/reception

finished

Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6

REQSL6

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA6 Software Request Generation Register

SIO1_TXD (transmit buffer empty)

When SIO1 transmit buffer is empty

CAN0_S0/S31

When CAN0 slot 0 transmission failed or slot 31 transmission/reception finished

Extended DMA6 transfer request

The source selected by the DMA6 Channel Control Register 1

source selected

(DM6CNT1) REQESEL6 bits (see below)

REQESEL6 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

One DMA5 transfer completed

When one DMA5 transfer is completed (cascade mode)

0001

MJT (TOU0_1irq)

MJT TOU0_1 interrupt source

0010

SIO1_RXD (reception completed)

When SIO1 reception is completed

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

DRI address counter 0 transfer completed

When DRI address counter 0 transfer completed

1110

DRI (DEC1_udf)

When DRI DEC1 underflow occurs

1111

Settings inhibited

–

9.3 Functional Description of DMAC

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