32186 datasheet(289/1032 Pages) RENESAS

289 / 1032 page

DMAC

9-43

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9

REQSL9

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start

When any data is written to the DMA9 Software Request Generation Register

SIO3_TXD (transmit buffer empty)

When SIO3 transmit buffer is empty

CAN1_S1/S30

When CAN1 slot 1 transmission failed or slot 30 transmission/reception

finished

Extended DMA9 transfer request

The source selected by the DMA9 Channel Control Register 1

source selected

(DM9CNT1) REQESEL9 bits (see below)

REQESEL9 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

One DMA8 transfer completed

When one DMA8 transfer is completed (cascade mode)

0001

MJT (TOU0_7irq)

MJT TOU0_7 interrupt source

0010

Settings inhibited

–

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

DRI transfer counter_udf

When DRI transfer counter underflow occurs

1110

DRI (DEC4_udf)

When DRI DEC4 underflow occurs

1111

DRI (DIN5)

When DRI DIN5 event detection interrupt is generated

9.3 Functional Description of DMAC

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