32186 datasheet(284/1032 Pages) RENESAS

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DMAC

9-38

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.3 Functional Description of DMAC

9.3.1 DMA Transfer Request Sources

For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There

are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request

from some internal peripheral I/O, in software by a program, or upon completion of one transfer or all

transfers on another DMA channel (cascade mode).

The causes or sources of DMA transfer requests are selected using the transfer request source select bits

REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request

source select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the

causes or sources of DMA transfer requests on each channel.

Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0

REQSL0

DMA Transfer Request Source

DMA Transfer Request Generation Timing

Software start or one DMA2

When any data is written to the DMA0 Software Request Generation

transfer completed

(cascade mode)

A/D0 conversion completed

When A/D0 conversion is completed

MJT (TIO8_udf)

When MJT TIO8 underflows

Extended DMA0 transfer request

The source selected by the DMA0 Channel Control Register 1

source selected

(DM0CNT1) REQESEL0 bits (see below)

REQESEL0 DMA Transfer Request Source

DMA Transfer Request Generation Timing

0000

MJT (input event bus 2)

When MJT input event bus 2 signal is generated

0001

MJT (TID0_udf/ovf)

When MJT TID0 underflow/overflow occurs

0010

CAN (CAN0_S0/S31)

When CAN0 slot 0 transmission failed or slot 31 transmission/reception

finished

0011

Common 1) MJT (input event bus 1)

When MJT input event bus 1 signal is generated

0100

Common 2) MJT (input event bus 3)

When MJT input event bus 3 signal is generated

0101

Common 3) MJT (output event bus 2)

When MJT output event bus 2 signal is generated

0110

Common 4) MJT (output event bus 3)

When MJT output event bus 3 signal is generated

0111

Common 5) A/D0 conversion completed

When A/D0 conversion is completed

1000

Common 6) MJT (TIN0S)

When MJT TIN0 input signal is generated

1001

Common 7) MJT (TIO8_udf)

When MJT TIO8 underflow occurs

1010

Common 8) MJT (TIN30S)

When MJT TIN30 input signal is generated

1011

Common 9) MJT (TIO9_udf)

When MJT TIO9 underflow occurs

1100

Common 10) Settings inhibited

–

1101

MJT (TOU1_0irq)

When MJT TOU1_0 interrupt request is generated

1110

DRI (DIN0)

When DRI DIN0 event detection interrupt is generated

1111

SIO4_TXD (transmit buffer empty)

When SIO4 transmit buffer empty interrupt is generated

9.3 Functional Description of DMAC

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