32186 datasheet(294/1032 Pages) RENESAS

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DMAC

9-48

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

9.3 Functional Description of DMAC

Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode

9.3.10 End of DMA and Interrupt

In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer

finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt

request is generated at completion of transfer. However, if interrupt requests on any channel have been

masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel.

During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until

the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests

are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests

generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.

9.3.11 Each Register Status after Completion of DMA Transfer

When DMA transfer is completed, the status of the source and destination address registers becomes as

follows:

(1) Address fixed

• The values set in the address registers before DMA transfer started remain intact (fixed).

(2) Address incremental

• For 8-bit transfer, the values of the address registers are the last transfer address + 1.

• For 16-bit transfer, the values of the address registers are the last transfer address + 2.

The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore,

before another DMA transfer can be performed, the transfer count register must be set newly again, except

when trying to perform transfers 65,536 times (H’FFFF).

Transfer count

Transfer address

H'0080 1000

H'0080 1001

H'0080 1002

H'0080 101E

H'0080 101F

↓

H'0080 1000

H'0080 1001

Transfer count

Transfer address

H'0080 1000

H'0080 1002

H'0080 1004

H'0080 103C

H'0080 103E

H'0080 1000

H'0080 1002

If the source address has been set to be incremented, it is the source address that recycles to the start

address; if the destination address has been set to be incremented, it is the destination address that

recycles to the start address. If both source and destination addresses have been set to be incremented,

both addresses recycle to the start address. However, the start address on either side must have their five

low-order bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000).

During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter

operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to

disable transfer).

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