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HD64F7047 Datasheet(PDF) 115 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 115 Page - Renesas Technology Corp |
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115 / 764 page ![]() Rev. 2.00, 09/04, page 75 of 720 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ3 I Input of maskable interrupt request signals Interrupt request output pin IRQOUT O Output of notification signal when an interrupt has occurred 6.3 Register Descriptions The interrupt controller has the following registers. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. • Interrupt control register 1 (ICR1) • Interrupt control register 2 (ICR2) • IRQ status register (ISR) • Interrupt priority register A (IPRA) • Interrupt priority register D (IPRD) • Interrupt priority register E (IPRE) • Interrupt priority register F (IPRF) • Interrupt priority register G (IPRG) • Interrupt priority register H (IPRH) • Interrupt priority register I (IPRI) • Interrupt priority register K (IPRK) |
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