HD64F7047 datasheet(119/764 Pages) RENESAS

119 / 764 page

Rev. 2.00, 09/04, page 79 of 720

6.3.3

IRQ Status Register (ISR)

ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins

IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be

withdrawn by writing 0 to IRQnF after reading IRQnF = 1.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

IRQ0F

IRQ1F

IRQ2F

IRQ3F

R/W

IRQ0 to IRQ3 Flags

These bits display the IRQ0 to IRQ3 interrupt request

status.

[Setting condition]

• When interrupt source that is selected by ICR1

and ICR2 has occurred.

[Clearing conditions]

• When 0 is written after reading IRQnF = 1

• When interrupt exception processing has been

executed at high level of

IRQn input under the low

level detection mode.

• When IRQn interrupt exception processing has

been executed under the edge detection mode of

falling edge, rising edge or both of falling and

rising edge.

• When the DISEL bit of DTMR of DTC is 0, after

DTC has been started by IRQn interrupt.

3 to 0



All 0

R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

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