HD64F7047 datasheet(122/764 Pages) RENESAS

122 / 764 page

Rev. 2.00, 09/04, page 82 of 720

6.4

Interrupt Sources

6.4.1

External Interrupts

There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral

modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and

16 the highest). Giving an interrupt a priority level of 0 masks it.

NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin

is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1)

to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt

mask level bits (I3 to I0) in the status register (SR) to level 15.

IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins

IRQ0 to IRQ3. Set

the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register 1 (ICR1) and IRQ

edge select bit (IRQ0ES[1:0] to IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select

low level detection, falling edge detection, or rising edge detection for each pin. The priority level

can be set from 0 to 15 for each pin using the interrupt priority registers A (IPRA).

When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC

during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when

the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ

flags (IRQ0F to IRQ3F) of the IRQ status register (ISR).

When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the

INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for

IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to

confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to

IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request

detection results can be withdrawn.

In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR)

are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block

diagram of this IRQ3 to IRQ0 interrupts.

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