HD64F7047 datasheet(124/764 Pages) RENESAS

124 / 764 page

Rev. 2.00, 09/04, page 84 of 720

6.5

Interrupt Exception Processing Vectors Table

Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt

priorities.

Each interrupt source is allocated a different vector number and vector table address offset. Vector

table addresses are calculated from the vector numbers and address offsets. In interrupt exception

processing, the exception service routine start address is fetched from the vector table indicated by

the vector table address. For the details of calculation of vector table address, see table 5.4,

Calculating Exception Processing Vector Table Addresses in the section 5 Exception Processing.

IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and

15 for each pin or module by setting interrupt priority registers A, D to I, K (IPRA, IPRD to IPRI,

IPRK). However, the smaller vector number has interrupt source, the higher priority ranking is

assigned among two or more interrupt sources specified by the same IPR, and the priority ranking

cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip

peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources

and interrupts from those sources occur simultaneously, they are processed by the default priority

order indicated in table 6.2.

HD64F7047 Datasheet(PDF) 124 Page - Renesas Technology Corp