HD64F7047 datasheet(123/764 Pages) RENESAS

123 / 764 page

Rev. 2.00, 09/04, page 83 of 720

IRQnS

IRQnES

ISR.IRQnF

IRQ pins

RESIRQn

Level

detection

Edge

detection

CPU interrupt

request

DTC

DTC starting request

(Acceptance of IRQn interrupt/DTC transfer end/

writing 0 after reading IRQnF = 1)

Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control

6.4.2

On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral

modules.

As a different interrupt vector is assigned to each interrupt source, the exception service routine

does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be

assigned to individual on-chip peripheral modules in interrupt priority registers A, D to I, K

(IPRA, IPRD to IPRI, IPRK). On-chip peripheral module interrupt exception processing sets the

interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-

chip peripheral module interrupt that was accepted.

6.4.3

User Break Interrupt

A user break interrupt has a priority of level 15, and occurs when the break condition set in the

user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are

held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3

to I0) in the status register (SR) to level 15. For more details about the user break interrupt, see

section 7, User Break Controller (UBC).

6.4.4

H-UDI Interrupt

High-performance user debugging interface (H-UDI) interrupt has a priority level of 15, and

occurs when an H-UDI interrupt instruction is serially input. H-UDI interrupt requests are detected

by edge and are held until accepted. H-UDI exception processing sets the interrupt mask level bits

(I3-I0) in the status register (SR) to level 15. For more details about the H-UDI interrupt, see

section 22, High-Performance User Debug Interface (H-UDI).

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