HD64F7047 datasheet(117/764 Pages) RENESAS

117 / 764 page

Rev. 2.00, 09/04, page 77 of 720

Bit

Bit Name

Initial

Value

R/W

Description

IRQ2S

R/W

IRQ2 Sense Select

This bit sets the IRQ2 interrupt request detection

mode.

0: Interrupt request is detected on low level of IRQ2

input

1: Interrupt request is detected on edge of IRQ2 input

(edge direction is selected by ICR2)

IRQ3S

R/W

IRQ3 Sense Select

This bit sets the IRQ3 interrupt request detection

mode.

0: Interrupt request is detected on low level of IRQ3

input

1: Interrupt request is detected on edge of IRQ3 input

(edge direction is selected by ICR2)

3 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

6.3.2

Interrupt Control Register 2 (ICR2)

ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins

IRQ0

IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the

edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1

(ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the

setting of ICR2 is ignored.

Bit

Bit Name

Initial

Value

R/W

Description

IRQ0ES1

IRQ0ES0

R/W

This bit sets the IRQ0 interrupt request edge

detection mode.

00: Interrupt request is detected on falling edge of

IRQ0 input

01: Interrupt request is detected on rising edge of

IRQ0 input

10: Interrupt request is detected on both of falling and

rising edge of

IRQ0 input

11: Cannot be set

HD64F7047 Datasheet(PDF) 117 Page - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 117 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL